`timescale 1ns/1ps
`default_nettype none

/* NOTE:
* - 对port端口进行水平偏移
*/

module cxy_port_offset (
    // system signal
    input  wire         I_sclk,  // 125M
    input  wire         I_rst_n,
    // config
    input  wire [7:0]   I_cfg_port_height,
    // port map
    output wire         O_port_map_rden,
    output wire [7:0]   O_port_map_addr,
    input  wire [15:0]  I_port_map_q,
    // input pixel
    input  wire         I_line_start,  // 行开始
    input  wire         I_line_end,    // 行结束
    input  wire [9:0]   I_line_num,    // 行号
    input  wire         I_pixel_valid, // 像素有效
    input  wire [9:0]   I_pixel_col,   // 像素列坐标
    input  wire [23:0]  I_pixel_gray,  // 像素数据
    // output pixel
    output wire         O_line_start,  // 行开始
    output wire         O_line_end,    // 行结束
    output wire [9:0]   O_line_num,    // 行号
    output wire         O_pixel_valid, // 像素有效
    output wire [9:0]   O_pixel_col,   // 像素列坐标
    output wire [23:0]  O_pixel_gray   // 像素数据
    );
//------------------------Parameter----------------------

//------------------------Local signal-------------------
wire [9:0]  quotient;
reg  [4:0]  virtual_port_id;
reg  [9:0]  port_offset;

reg  [3:0]  line_start_sr;
reg  [3:0]  line_end_sr;
reg  [3:0]  pixel_valid_sr;

reg  [9:0]  line_num_sr0;

reg  [9:0]  pixel_col_sr0;
reg  [9:0]  pixel_col_sr1;
reg  [9:0]  pixel_col_sr2;

reg  [23:0] pixel_gray_sr0;
reg  [23:0] pixel_gray_sr1;
reg  [23:0] pixel_gray_sr2;
reg  [23:0] pixel_gray_sr3;

reg  [9:0]  pixel_col;

//------------------------Instantiation------------------
div_10_8 div(
    .numer          (I_line_num         ),
    .denom          (I_cfg_port_height  ),
    .quotient       (quotient           ),
    .remain         (                   )
    );

//------------------------Body---------------------------
//virtual_port_id[4:0]
always@(posedge I_sclk)
    if(line_start_sr[0])
        virtual_port_id <= quotient[4:0];

assign O_port_map_rden = 1'b1;
assign O_port_map_addr = {3'b000,virtual_port_id[4:0]};

//port_offset[9:0]
always@(posedge I_sclk)
    if(line_start_sr[2])
        port_offset <= I_port_map_q[15:6];

//pixel_col[9:0]
always@(posedge I_sclk)
    if(pixel_valid_sr[2])
        pixel_col <= port_offset[9] ? (pixel_col_sr2 - port_offset[8:0]) : (pixel_col_sr2 + port_offset[8:0]);

always@(posedge I_sclk)
    begin
        line_start_sr  <= {line_start_sr [2:0],I_line_start };
        line_end_sr    <= {line_end_sr   [2:0],I_line_end   };
        pixel_valid_sr <= {pixel_valid_sr[2:0],I_pixel_valid};

        line_num_sr0   <= I_line_num;

        pixel_col_sr0  <= I_pixel_col;
        pixel_col_sr1  <= pixel_col_sr0;
        pixel_col_sr2  <= pixel_col_sr1;

        pixel_gray_sr0 <= I_pixel_gray;
        pixel_gray_sr1 <= pixel_gray_sr0;
        pixel_gray_sr2 <= pixel_gray_sr1;
        pixel_gray_sr3 <= pixel_gray_sr2;
    end
//-------------------------------------------------------
assign O_line_start  = line_start_sr [3];
assign O_line_end    = line_end_sr   [3];
assign O_pixel_valid = pixel_valid_sr[3];
assign O_pixel_gray  = pixel_gray_sr3;

assign O_line_num    = line_num_sr0;
assign O_pixel_col   = pixel_col;
//-------------------------------------------------------
endmodule

`default_nettype wire

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